The figure that should reorganize how the industry thinks about compute scarcity is 30,000. That is the approximate monthly wafer-equivalent output of TSMC's CoWoS advanced packaging lines at the close of 2025. Every Blackwell shipped to a hyperscaler, every Hopper still being retrofitted into inference clusters, every AMD MI300 and MI325 in a Lisa Su keynote, every Google TPU v5p exiting Hsinchu, every Rubin sample in NVIDIA's pre-production queue passes through that 30,000-wafer monthly throughput. TSMC has guided the number toward 60,000 to 80,000 by end of 2026. Demand, by the same internal estimates that move through the supply chain, is north of 100,000 wafer-equivalents and rising. NVIDIA alone has reserved a share of available capacity that industry trackers place above fifty percent, with some quarters running closer to sixty.
This is the binding constraint on global AI compute. Not fab capacity. Not EUV scanners. Not HBM stack supply, though that is tight. Not interconnection queues at PJM or ERCOT, though those receive most of the trade-press attention. The single industrial process that cannot be substituted, parallelized across vendors, or accelerated by capital injection is Chip-on-Wafer-on-Substrate packaging, and it is performed at meaningful volume in exactly three facilities in Taiwan and one nascent expansion in Arizona.
The chokepoint upstream of every GPU is the chokepoint upstream of every campus.
The Process Nobody Maps
CoWoS is not a chip. It is the assembly stage that turns a logic die and a stack of high-bandwidth memory into a single functional accelerator. A finished H100 or B200 is not one piece of silicon. It is a logic die produced on a 4nm or 3nm node, several HBM3 or HBM3e stacks produced by SK Hynix, Samsung, or Micron, and a silicon interposer that wires them together with bandwidths that conventional substrate routing cannot achieve. The interposer is the load-bearing structure. Without it, the logic die cannot talk to the memory at the rates that make modern training workloads tractable.
The interposer is fabricated on a silicon wafer using lithography steps adjacent to but distinct from logic fabrication. The dies are then placed onto the interposer at micron-level precision. The interposer-plus-dies assembly is then bonded to an organic substrate. The substrate is fabricated from Ajinomoto Build-up Film, a dielectric material produced almost exclusively by Ajinomoto Fine-Techno in Japan. The finished package is then tested, burned in, and shipped.
None of these steps can be skipped. None of them can be performed by a conventional outsourced semiconductor assembly and test house at the volumes and yields required for a $30,000 accelerator. CoWoS is a process recipe, a tooling configuration, a cleanroom buildout, a yield-learning curve, and a vendor-qualification ladder that took TSMC roughly a decade to scale. The recipe is proprietary. The tooling is partially custom. The yield learning is non-transferable.
Three variants matter. CoWoS-S uses a silicon interposer and is the workhorse for current Hopper and Blackwell volumes. CoWoS-R substitutes an organic redistribution layer for the silicon interposer at lower bandwidth but better cost. CoWoS-L, the variant targeting Rubin-class parts, uses a local silicon interconnect bridge inside a larger organic carrier and is the path toward packages that exceed the reticle limit of a single interposer. Each variant has its own yield curve, its own tooling, its own qualification cycle. Capacity stated as a single CoWoS number obscures the fact that the specific variant a customer needs may be tighter than the aggregate.
The Three Sites
Advanced packaging at the volumes that matter happens at three TSMC facilities. AP3 in Chunan, the original CoWoS line, has been the bring-up site for every major node transition. AP5 in Tainan is the volume expansion that brought capacity from sub-10,000 wafers per month in 2023 to the 30,000 range by late 2025. AP6 in Longtan, breaking ground through 2024 and ramping through 2026, is the structural expansion that the 60,000 to 80,000 end-of-2026 guidance depends on. A fourth site, AP7, has been disclosed for further expansion late in the decade.
The Arizona expansion announced in 2024 and elaborated in 2025 adds a second geography. TSMC's Phoenix campus, originally planned around logic fabrication, has been expanded to include advanced packaging in response to direct customer pressure and CHIPS Act incentives. The packaging volume scheduled to come online in Arizona through 2027 and 2028 is meaningful at the margin but does not change the structure of the constraint within the 2026 to 2028 window. The qualification, ramp, and yield-learning cycle on a new geography runs years, not quarters.
Amkor and ASE Group, the two largest independent assembly and test providers, have been picking up secondary advanced packaging volumes. Amkor's Vietnam and Korea facilities and ASE's Taiwan and Malaysia operations have qualified processes that approximate CoWoS for specific customers and specific products. The capacity is real and growing. It is also several quarters behind TSMC on the yield-learning curve for the highest-performance variants, and the largest hyperscaler customers have shown a strong preference for TSMC-packaged parts when both are available. The secondary capacity relieves pressure at the edges of the market. It does not relieve pressure at the center.
Who Has Reserved What
NVIDIA's CoWoS reservations through 2026 sit at a share that industry estimates place between fifty and sixty percent of available capacity. The reservation is not a contract in the conventional sense. It is a multi-year capacity commitment that combines prepayments, take-or-pay structures, and a level of operational integration with TSMC's planning cycle that effectively crowds out spot demand. When a hyperscaler customer asks NVIDIA for additional B200 or B300 units, NVIDIA's binding constraint on the answer is its CoWoS allocation, not its design pipeline.
AMD's MI300X and MI325X volumes through 2026 are gated by a CoWoS allocation that is smaller than NVIDIA's by roughly an order of magnitude. The product is competitive on raw silicon. The supply constraint is the packaging line. AMD has been working through Amkor for secondary capacity on specific variants and has shifted parts of its roadmap to packaging approaches that reduce CoWoS dependence. The MI350 series, scheduled for late 2026, is the first AMD part designed from the start around a multi-vendor packaging strategy.
Google's TPU v5p shipped on TSMC advanced packaging through 2024 and 2025. The v6 generation, the Trillium successor, depends on CoWoS-L for the multi-die configurations that Google has signaled for its 2026 training fleet. Google's packaging allocation is a negotiated number that sits below NVIDIA's share but above most other customers, reflecting Google's role as a long-standing TSMC customer with co-developed process IP.
Apple is the structural complication. Apple's M-series and the A-series Pro variants use CoWoS-S and CoWoS-R for the high-end SKUs. Apple's volumes are not AI accelerators in the data-center sense, but they consume the same packaging lines, qualify for similar variants, and have first-mover allocation rights in TSMC's customer hierarchy that predate the AI buildout. Broadcom's custom ASICs, including the parts produced for Google's TPU program and for several other hyperscaler custom-silicon efforts, occupy another large block of the available capacity.
The arithmetic is straightforward. NVIDIA, AMD, Google through Broadcom, Apple, and the remaining hyperscaler custom-silicon programs together reserve essentially all of TSMC's CoWoS capacity through 2026 and into 2027. The marginal customer with a credible accelerator design and a willingness to pay above market for capacity finds that there is no market. The capacity has been forward-sold.
The Materials Layer Beneath
A silicon interposer is fabricated on the same wafer infrastructure as a logic die, which means interposer capacity competes with logic capacity at the wafer level even before the assembly step. TSMC has been allocating interposer wafer starts inside its mature-node fabs, which trades off against automotive, industrial, and consumer-electronics customers who use the same nodes. The interposer wafer constraint is one of the reasons the path from 30,000 to 80,000 monthly throughput requires capital, time, and yield work that cannot be compressed.
ABF substrate is the layer beneath the interposer. Ajinomoto, the Japanese food and chemicals company whose monosodium glutamate process produced the polymer chemistry behind the substrate, holds approximately the entire global supply. Several attempted entrants have failed to qualify at the performance levels required for advanced packaging. Ajinomoto's capacity expansion has been steady but not aggressive. The ABF supply chain runs through Japan, with downstream substrate fabrication concentrated in Taiwan, Korea, and Japan.
The materials layer is the second-order constraint. Even if TSMC doubled CoWoS line capacity tomorrow, the substrate supply chain would gate the output for several quarters. The Korea HBM supply chain, dominated by SK Hynix with Samsung in second position, is a third-order constraint that has received more press attention but is structurally easier to relieve than ABF, because there are at least three credible HBM producers and there is functionally one ABF producer.
The Bessemer Parallel
In the 1860s and 1870s, steel production in the United States and Britain was not gated by iron ore or by coal. Both were abundant. The binding constraint was the Bessemer converter, a vessel that blew air through molten pig iron to burn off carbon and produce steel at industrial volumes. The converter was a specific process recipe with a specific yield curve and a specific licensing structure. Henry Bessemer held the patents in Britain. In the United States, Andrew Carnegie understood earlier than his competitors that the converter, not the ore, was the asset.
Carnegie's strategy at the Edgar Thomson works was to control converter capacity. He bought the licenses, he hired the engineers who understood the yield curve, he built the largest converter installations in the country at a moment when his competitors were still investing in ore and rail. When the price of steel fell through the 1870s and 1880s, Carnegie's converter-cost advantage compounded. Competitors with more ore and more capital but less converter capacity lost share through every cycle.
The CoWoS situation is the converter situation. Silicon design talent is abundant. Wafer fabrication capacity at leading nodes is constrained but not uniquely so. The binding step is the assembly recipe that took a decade to learn, the tooling that cannot be duplicated by buying machines, and the customer-qualification ladder that locks in the largest buyers. The party that controls that step controls the throughput of the industry it feeds.
NVIDIA's reservation of CoWoS capacity is the modern equivalent of Carnegie's converter strategy, executed inside a different industrial structure. NVIDIA does not own the line. It owns the priority claim on the line. The economic effect is similar.
What Becomes True By 2028
Three projections follow from the structure.
First, advanced packaging capacity becomes a publicly tracked strategic asset on the level that EUV scanner deliveries became tracked through the late 2010s. The figures that today circulate inside semiconductor analyst notes appear in government policy documents, in earnings call disclosures from hyperscaler buyers, and in trade negotiations between the United States, Taiwan, Japan, and Korea. The CoWoS capacity number becomes a sovereign-level data point.
Second, CHIPS Act 2.0 or its functional equivalent directs material funding specifically toward US advanced packaging capacity. The first CHIPS Act prioritized leading-edge logic and assumed packaging would follow. The structural lesson of the 2025 to 2027 supply situation is that packaging does not automatically follow logic, that the recipe and the yield-learning curve are sovereign-grade industrial assets, and that the United States cannot underwrite its AI compute position without onshore packaging at scale. Amkor's Arizona expansion, ASE's potential US footprint, and TSMC's Phoenix packaging buildout all become recipients of policy attention disproportionate to their current revenue scale.
Third, data-center campus underwriting begins to include GPU access through 2028 as an explicit, documented variable in the diligence package. The current diligence stack covers power, water, fiber, entitlements, tax structure, and labor. It does not cover whether the operator can secure the chips to fill the racks. By 2027 it will, because the gap between announced campus capacity and deliverable chip volume becomes large enough that the lenders financing the campuses require it. The campus that can document a path to chip supply through 2028 trades at a premium to the campus that cannot. The packaging allocation, several layers upstream, becomes part of the real-estate underwriting.
The convergence of these three projections produces an industry in which the location of advanced packaging capacity, the identity of its customers, and the share-of-line each customer holds are first-order strategic facts. Allied governments negotiate packaging supply guarantees the way they once negotiated petroleum access. The Bessemer analogy holds through the second derivative. Carnegie's converter became, by the 1890s, a question of national industrial policy. CoWoS is on the same trajectory, compressed into a shorter cycle.
The constraint that today appears in the footnotes of NVIDIA's earnings calls becomes, by 2028, the variable that organizes the conversation.