The CoWoS bottleneck is the constraint that everyone now talks about. Two thousand four hundred-millimeter wafers per month at TSMC, divided across NVIDIA, AMD, Broadcom, and a handful of hyperscaler custom silicon programs, set the upper bound on how many accelerators reach customers in 2026. That story is correct as far as it goes. It does not go far enough.
Downstream of the advanced packaging line sits a second constraint that is harder to scale, controlled by fewer firms, and structurally more difficult to expand. High-bandwidth memory, the stacked DRAM that sits beside the GPU die on the same interposer, has moved from a niche product line to the single most strategically scarce component in the AI supply chain. In 2023, HBM represented less than five percent of total DRAM industry revenue. By 2026, on current trajectory, it crosses twenty-five percent. The product line that did not matter to the memory industry a half-decade ago now sets the price, the margin, and the production priority of every fab decision the three remaining DRAM manufacturers make.
There are three of them. That is the number to hold in mind. SK Hynix, Samsung, and Micron supply effectively all HBM3 and HBM3e in the world. No fourth player exists at scale. No Chinese entrant has qualified at NVIDIA. No new fab anywhere on Earth will produce qualified HBM3e for a customer that did not already buy from one of the three by 2024. Without their output, the most expensive silicon ever manufactured is silicon without working memory, and inference and training throughput collapses to the bandwidth of whatever DDR or GDDR product can be glued on instead, which is to say, to a small fraction of what the accelerator was designed to deliver.
Three Firms Stack The Memory
SK Hynix holds the dominant share of HBM supply into NVIDIA Blackwell. Industry tracking through the first half of 2026 places the Korean firm at roughly half of total HBM3e output and a larger share of the volume that ships into NVIDIA's flagship platform. The company qualified its 12-high HBM3e stacks for Blackwell ahead of either competitor and signed multi-year supply commitments that locked the majority of its 2025 and 2026 capacity before either Samsung or Micron had completed customer qualification at the same node.
Micron occupies the second position by volume into NVIDIA and the only US-domiciled HBM production at scale. The company's Idaho HBM3e ramp, supported by CHIPS Act funding, brought the first non-Korean qualified supply online during 2024 and expanded through 2025. Micron's share of the Blackwell HBM3e socket is meaningfully smaller than SK Hynix's, but the geographic position matters more than the share number suggests. For US-domiciled hyperscalers and for any sovereign tenant evaluating supply chain resilience, Micron is the only HBM source that does not require Korean export from a Korean fab.
Samsung holds the third position and has spent the better part of two years working through the qualification challenges that delayed its 12-high HBM3e stacks at NVIDIA. The qualification difficulty is itself a structural fact: Samsung is the largest DRAM manufacturer in the world by total bit output, and the qualification gap on HBM persisted into 2026. The company holds substantial share with AMD and with Chinese customers where US export control and NVIDIA qualification do not bind, but its position into the Blackwell socket is the smallest of the three. Samsung's HBM4 roadmap is the most aggressive of the three, and the gap could close at the next node. It has not closed yet.
The combined production of these three firms is the entire world supply. There is no fourth.
Why The Yield Curve Matters
HBM is not faster DRAM in a different package. It is stacked DRAM, where eight or twelve or sixteen dies are bonded vertically and connected through holes etched directly through the silicon. The technique is called through-silicon via, or TSV, and it is the reason the yield curve on HBM does not look like the yield curve on any other memory product.
A conventional DDR5 die yields well because failure is localized. A single defective bit can be repaired through redundancy, and the cost of a defective die is the cost of one die. A twelve-high HBM3e stack does not yield well because failure propagates. A defective die in the middle of the stack ruins the eleven good dies bonded to it. The TSV connection itself, which requires hundreds or thousands of vertical interconnects per die at micron-scale precision, introduces a failure mode that does not exist in planar memory at all. Industry yield on the latest HBM3e nodes is substantially below the yield on DDR5 at the same lithography, and the gap widens with each additional layer in the stack.
The transition now underway from twelve-high to sixteen-high stacks compounds the problem. Sixteen-high stacks deliver the bandwidth and capacity that HBM4 promises, and they yield meaningfully worse than twelve-high. The R&D investment required to bring sixteen-high yields to commercially acceptable levels is the dominant capital story inside all three manufacturers' 2026 plans. SK Hynix has guided to HBM4 commercial volume in 2026 with broader ramp in 2027. Samsung has been more aggressive on timing and less specific on volume. Micron has been the most conservative on schedule and the most specific on which customer qualifications it expects to complete.
The TSV supply chain itself is narrow. The equipment that drills, fills, and bonds the through-silicon vias comes from a small set of vendors: Applied Materials, ASMPT, KLA, Disco, Tokyo Electron, and a handful of specialist Japanese and Korean firms. Capacity expansion at any HBM manufacturer is gated by tool delivery from this set, which is gated in turn by ABF substrate availability, which is the same Ajinomoto bottleneck that constrains CoWoS at the advanced packaging stage. The two constraints share a common upstream input.
The capex to enter HBM is approximately four to eight billion dollars per fab, before tool delivery delays. The number of new entrants over the past five years is zero. The number of new entrants expected over the next five years, outside of capacity expansion by the existing three, is also zero.
What Sold Out Already Means
SK Hynix reported in 2024 that its HBM3e output was fully committed through 2025. In 2025 it reported that it was fully committed through 2026. Samsung and Micron have followed the same pattern at slightly different timelines. The forward supply curve for HBM3e is, in commercial terms, closed. A new buyer entering the market in 2026 cannot purchase additional volume at any price; they can only purchase volume that another buyer has released, which essentially does not happen because every existing buyer is short.
This matters because the demand side is not flattening. Blackwell shipments through 2026, the AMD MI350 and MI400 ramp, the custom silicon programs at Google, Amazon, Microsoft, and Meta, and the Chinese domestic accelerator buildout all draw from the same HBM pool. The aggregate HBM demand from these programs exceeds the aggregate qualified HBM3e supply by a margin that the three manufacturers' published expansion plans do not close. HBM4, which would relieve the pressure, slips into 2026 commercial volume with broader ramp in 2027, which means the bridge year is structurally short.
The pricing follows. HBM3e stacks have traded at multi-thousand-dollar-per-stack levels for the past eighteen months, against legacy DDR5 module pricing that is one or two orders of magnitude lower per gigabyte. The margin contribution of HBM to the three manufacturers' earnings has gone from immaterial to dominant in the span of six quarters. SK Hynix passed Samsung in DRAM operating profit for the first time in the company's history during this period, driven entirely by HBM mix.
When a product line that represents twenty-five percent of an industry's revenue is sold out two years forward and is the dominant earnings contributor for the three firms that make it, the structural posture of the industry has changed. HBM is no longer a memory product. It is an allocation regime.
The Coke Parallel
The industrial precedent is steel, and the lesson is Carnegie's. Iron ore was the visible input to steel production through the late nineteenth century. It was tracked, traded, and reported on in the financial press. Coke, the refined coal product required to fuel the blast furnace at the temperatures and chemistries that produced quality steel, was less discussed. It was also harder to scale. Coke ovens required specific coal grades, long capital lead times, and process discipline that newer entrants could not replicate at quality.
Andrew Carnegie understood that the constraint on his steel output was not iron ore. It was coke. In 1882, he vertically integrated into the Frick Coke Company, securing the coke supply that competitors could not match at price or volume. The cost dominance that followed was not a marketing advantage. It was a structural advantage that compounded for two decades and underwrote the formation of US Steel.
HBM is the coke of the AI age. CoWoS, GPU silicon, and accelerator design are the visible constraints. They attract the financial press coverage, the equity research notes, and the policy attention. HBM is less discussed, harder to scale, and controlled by a smaller number of firms. The party that secures HBM supply ahead of its competitors does not gain a marketing advantage. It gains a structural advantage that compounds across product cycles.
NVIDIA understood this earlier than its peers. The multi-year HBM3e supply commitments that locked SK Hynix's capacity through 2026 were not procurement decisions. They were a Frick Coke moment, executed by Jensen Huang's organization at a moment when the rest of the industry was still focused on the more visible packaging constraint.
What Becomes True By 2028
HBM capacity will be a publicly tracked strategic variable by 2028, comparable to oil reserves or rare earth mineral output. The disclosure pressure is already building. Sovereign tenants underwriting multi-gigawatt data center buildouts in the US, the Gulf, Europe, and Asia are beginning to write HBM supply commitments into their compute offtake agreements, which means the bilateral supply relationship between the three HBM manufacturers and the largest AI infrastructure buyers becomes a matter of formal policy interest.
The South Korea-US axis in memory will be codified. Two of the three HBM manufacturers are Korean. The third is American. The export control posture toward Chinese HBM access, which has tightened in incremental steps since 2023, becomes a formal supply relationship that resembles in structure the petroleum reserve coordination of an earlier era. Korean HBM output is, in commercial terms, an extension of US compute capacity. Both governments behave accordingly.
CHIPS Act 2.0 funding, or its functional equivalent, flows toward US-domiciled HBM expansion. Micron's Idaho ramp is the template. Additional fabs in New York and elsewhere come under active consideration through 2027 with construction commitments through 2028. The political economy of memory production becomes a topic that congressional staff understand in detail, which is a sentence that would have been inconceivable in 2020.
HBM4 commercial volume ramps through 2027 and reaches scale in 2028. The bridge year between HBM3e exhaustion and HBM4 abundance is the structurally tightest window in the AI hardware supply chain, and it falls in 2026 and 2027. The companies that secured supply ahead of that window operate at full capacity. The companies that did not operate at the capacity that the spot market allows, which is less.
The industry will eventually expand out of the constraint. It always does. The question that matters in the meantime is which buyers and which sovereigns are positioned for the eighteen months during which the constraint binds hardest. The answer to that question is being negotiated now, in supply agreements that are not public and in capacity allocations that are not disclosed, and it determines how much intelligence the world ships next year.
The coke ovens were not the story of the steel age. They decided it.
Autonomous Industries Insights is the research arm of Autonomous Industries AI. Industrial AI coverage focuses on the physical infrastructure constraints that determine the pace of artificial intelligence deployment.